1 extended commercial temperature range idt74alvch16701 3.3v cmos 18-bit read/write buffer with bus-hold features: C 0.5 micron cmos technology C typical t sk(0) (output skew) < 250ps C esd > 2000v per mil-std-883, method 3015; > 200v using machine model (c = 200pf, r = 0) C 0.635mm pitch ssop, 0.50mm pitch tssop, and 0.40mm pitch tvsop packages C extended commercial range of C 40c to + 85c Cv cc = 3.3v 0.3v, normal range Cv cc = 2.7v to 3.6v, extended range Cv cc = 2.5v 0.2v C cmos power levels (0.4 w typ. static) C rail-to-rail output swing for increased noise margin description: september 1999 1999 integrated device technology, inc. dsc-4222/- c idt74alvch16701 extended commercial temperature range 3.3v cmos 18-bit read/write buffer with bus-hold applications: ? 3.3v high speed systems ? 3.3v and lower voltage computing systems functional block diagram drive features for alvch16701: C high output drivers: 24ma C suitable for heavy loads this 18-bit read/write buffer is built using advanced dual metal cmos technology. the alvch16701 is equipped with a four deep fifo and a read-back latch. it can be used as a read/write buffer between a cpu and a memory or to interface a high-speed bus and a slow peripheral. the a-to-b (write) path has a four deep fifo for pipelined operations. the fifo can be reset and a fifo full condition is indicated by the full flag (ff). the b-to-a (read) path has a latch. the alvch16701 has been designed with a 24ma output driver. this driver is capable of driving a moderate to heavy load while maintaining speed performance. the alvch16701 has bus-hold which retains the inputs last state whenever the input goes to a high impedance. this prevents floating inputs and eliminates the need for pull-up/down resistor. b 1:18 ff clk reset oeab wce rce fifo (4 deep) 18 oeba le latch a 1:18 18 29 55 2 56 30 27 28 1
2 extended commercial temperature range idt74alvch16701 3.3v cmos 18-bit read/write buffer with bus-hold absolute maximum rating (1) symbol description max. unit v term (2) terminal voltage with respect to gnd C 0.5 to + 4.6 v v term (3) terminal voltage with respect to gnd C 0.5 to v cc + 0.5 v t stg storage temperature C 65 to + 150 c i out dc output current C 50 to + 50 ma i ik continuous clamp current, v i < 0 or v i > v cc 50 ma i ok continuous clamp current, v o < 0 C 50 ma i cc i ss continuous current through each v cc or gnd 100 ma new16link notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. v cc terminals. 3. all terminals except v cc . capacitance (t a = +25 o c, f = 1.0mhz) symbol parameter (1) conditions typ. max. unit c in input capacitance v in = 0v 5 7 pf c out output capacitance v out = 0v 7 9 pf c i/o i/o port capacitance v in = 0v 7 9 pf new16link note: 1. as applicable to the device type. c pin configuration ssop/ tssop/tvsop top view so56-1 so56-2 so56-3 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 48 49 50 51 52 53 54 55 56 1 25 26 27 28 32 31 30 29 gnd v cc gnd gnd v cc gnd reset rce clk b 1 b 2 b 3 b 4 b 5 b 6 b 7 b 8 b 10 b 11 b 12 b 9 b 13 b 14 b 15 b 16 b 17 b 18 ff oeab gnd v cc a 4 gnd gnd v cc a 15 gnd wce a 1 a 2 a 3 a 5 a 6 a 7 a 8 a 9 a 10 a 11 a 12 a 13 a 14 a 16 a 17 a 18 oeba le
3 extended commercial temperature range idt74alvch16701 3.3v cmos 18-bit read/write buffer with bus-hold function table (1) note: 1. h = high voltage level l = low voltage level x = dont care - = low-to-high transition pin description function description this device is useful as a read/write buffer for modular high end designs. it provides multi-level buffering in the write path and single deep buffering in the read path, and is suited to write back cache implementation. the read path provides a transparent latch. the four deep fifo uses one clock with two clock enable pins, wce and rce to clock data in and out. the fifo has an external full flag which goes low when the fifo is full. internal read and write pointers keep track of the words stored in the fifo. a write attempt to a full fifo is ignored. an attempt read from an empty fifo will have no effect and the last read data remains at the output of the fifo. inputs outputs notes oeba oeab le reset clk ax bx hhhh - q(b) bus hold q 0 (a) -4clks bus hold lhhh - b to a transparent mode lh l h - q 0 (b) hh x h - q 0 (a) bus hold q 0 (b) bus hold hl xh - a to b - 4 clks ll lh - q 0 (b) bus hold q 0 (b) - 4 clks bus hold case not recommended note: 1. these pins have bus-hold. all other pins are standard inputs, outputs, or i/os. the fifo may be reset by the synchronous reset input. this resets the read and write pointers to the original empty condition and also sets all b outputs = 1. simultaneous read and write attempts (clock data into fifo as well as clock data out of fifo) are possible except on fifo empty and full boundaries. when the fifo is empty, and a simultaneous read and write is attempted, the read is ignored while the write is executed. if the same is attempted when the fifo is full, the write is ignored while the read is executed. normal operation of the four deep fifo in the write path is independent of the read path operation. pin names i/o description a 1-18 i/o 18 bit i/o port (1) b 1-18 i/o 18 bit i/o port (1) clk i clock for write path fifo. clocks data into fifo when wce is low, clocks data out of fifo when rce is low. when fifo is f ull all further writes to the fifo are inhibited. when fifo is empty all reads from the fifo are inhibited. clk also resets the fifo when reset is low. wce i enable pin for fifo input clock. rce i enable pin for fifo output clock. ff o write path fifo full flag. goes low when fifo is full. reset i synchronous fifo reset - when low clk resets the fifo. the fifo pointers are initialized to the "empty" condition and fi fo output is forced high (all ones). the fifo full flag (ff) will be high immediately after reset. oeab i output enable pin for b port oeba i output enable pin for a port le i read path latch enable pin. when high, data flows transparently from b port to a port, b data is latched on the falling edg e of le.
4 extended commercial temperature range idt74alvch16701 3.3v cmos 18-bit read/write buffer with bus-hold dc electrical characteristics over operating range following conditions apply unless otherwise specified: operating condition: ta = C 40c to +85c symbol parameter test conditions min. typ. (1) max. unit v ih input high voltage level v cc = 2.3v to 2.7v 1.7 v v cc = 2.7v to 3.6v 2 v il input low voltage level v cc = 2.3v to 2.7v 0.7 v v cc = 2.7v to 3.6v 0.8 i ih input high current v cc = 3.6v v i = v cc 5a i il input low current v cc = 3.6v v i = gnd 5 i ozh high impedance output current v cc = 3.6v v o = v cc 10a i ozl (3-state output pins) v o = gnd 10 a v ik clamp diode voltage v cc = 2.3v, i in = C 18ma C 0.7 C 1.2 v v h input hysteresis v cc = 3.3v 100 mv i ccl i cch i ccz quiescent power supply current v cc = 3.6v v in = gnd or v cc 0.140a d i cc quiescent power supply current variation one input at v cc - 0.6v, other inputs at v cc or gnd 750 a new16lin k note: 1. typical values are at v cc = 3.3v, +25c ambient. timing diagram clk reset wce oeab a [1:18] ff b [1:18] rce word 1 word 2 word 3 word 4 word 1 word 2 word 3 word 4 write cycles cycle 1 cycle 2 cycle 3 cycle 4 cycle 1 cycle 2 cycle 3 cycle 4 read cycles
5 extended commercial temperature range idt74alvch16701 3.3v cmos 18-bit read/write buffer with bus-hold symbol parameter (1) test conditions min. typ. (2) max. unit i bhh bus-hold input sustain current v cc = 3.0v v i = 2.0v C 75 a i bhl v i = 0.8v 75 i bhh bus-hold input sustain current v cc = 2.3v v i = 1.7v C 45 a i bhl v i = 0.7v 45 i bhho bus-hold input overdrive current v cc = 3.6v v i = 0 to 3.6v 500 a i bhlo new16link bus-hold characteristics notes: 1. pins with bus-hold are identified in the pin description. 2. typical values are at v cc = 3.3v, +25c ambient. output drive characteristics note: 1. v ih and v il must be within the min. or max. range shown in the dc electrical characteristics over operating range table for the appropriate v cc range. t a = C 40c to + 85c. symbol parameter test conditions (1) min. max. unit v oh output high voltage v cc = 2.3v to 3.6v i oh = C 0.1ma v cc C 0.2 v v cc = 2.3v i oh = C 6ma 2 v cc = 2.3v i oh = C 12ma 1.7 v cc = 2.7v 2.2 v cc = 3.0v 2.4 v cc = 3.0v i oh = C 24ma 2 v ol output low voltage v cc = 2.3v to 3.6v i ol = 0.1ma 0.2 v v cc = 2.3v i ol = 6ma 0.4 i ol = 12ma 0.7 v cc = 2.7v i ol = 12ma 0.4 v cc = 3.0v i ol = 24ma 0.55 new16link operating characteristics, t a = 25 o c v cc = 2.5v 0.2v v cc = 3.3v 0.3v symbol parameter test conditions typical typical unit c pd power dissipation capacitance outputs enabled clk toggling 28 31 pf c l = 0pf, f = 10mhz one bit toggling 26 29 c pd power dissipation capacitance outputs enabled clk toggling 10 11 pf one bit toggling 9 10
6 extended commercial temperature range idt74alvch16701 3.3v cmos 18-bit read/write buffer with bus-hold switching characteristics (1) v cc = 2.7v v cc = 3.3v 0.3v parameter test conditions min. max. min. max. unit propagation delays 1b 1-18 to a 1-18 read path/latch 1.5 4.5 ns 2 le (low to high) to a 1-18 read path/latch 1.5 4.5 ns 3 clk to f f write path 1.5 5.5 ns 4 clk to b 1-18 write path 1.5 5.5 ns 5 output skew (2) write path 1 ns setup & hold times 6a 1-18 to clk (low to high) setup write path 1.8 ns 7a 1-18 to clk (low to high) hold write path 1 ns 8b 1-18 to le (high to low) setup read path/latch 1.8 ns 9b 1-18 to le (high to low) hold read path/latch 1 ns 10 wce , rce (low) to clk setup write path 3.5 ns 11 wce , rce (low) to clk hold write path 0.5 ns 12 reset (low) to clk setup write path 1.8 ns 13 reset (low) to clk hold write path 1 ns enable & disable times 14 oeba low to a 1-18 enable write path 1.5 6 ns 15 oeba high to a 1-18 disable write path 1.5 5.7 ns 16 oeab low to b 1-18 enable read path 1.5 6 ns 17 oeab high to b 1-18 disable read path 1.5 5.7 ns minimum pulse widths 18 clk high or low pulse width write path 5 ns 19 le high pulse width read path/latch 5 ns 19 clock frequency 83 mhz 20 clock cycle time 12 ns notes: 1. see test circuits and waveforms. t a = C 40c to + 85c. 2. skew between any two outputs of the same package and switching in the same direction.
7 extended commercial temperature range idt74alvch16701 3.3v cmos 18-bit read/write buffer with bus-hold open v load gnd v cc pulse generator d.u.t. 500 w 500 w c l r t v in v out (1, 2) alvc link input v ih 0v v oh v ol t plh1 t sk (x) output 1 output 2 t phl1 t sk (x) t plh2 t phl2 v t v t v oh v t v ol t sk (x) = t plh2 - t plh1 or t phl2 - t phl1 alvc link same phase input transition opposite phase input transition 0v 0v v oh v ol t plh t phl t phl t plh output v ih v t v t v ih v t alvc link data input 0v 0v 0v 0v t rem timing input synchronous control t su t h t su t h v ih v t v ih v t v ih v t v ih v t alvc link asynchronous control low-high-low pulse high-low-high pulse v t t w v t alvc link control input t plz 0v output normally low t pzh 0v switch closed output normally high enable disable switch open t phz 0v v lz v oh v t v t t pzl v load/2 v load/2 v ih v t v ol v hz alvc link notes: 1. for t sk (o) output1 and output2 are any two outputs. 2. for t sk (b) output1 and output2 are in the same bank. test cir cuits and w a veforms test conditions propagation delay test circuits for all outputs enable and disable times set-up, hold, and release times switch position output skew - tsk (x) symbol v cc (1) = 3.3v0.3v v cc (1) = 2.7v v cc (2) = 2.5v0.2v unit v load 662 x vccv v ih 2.7 2.7 vcc v v t 1.5 1.5 vcc / 2 v v lz 300 300 150 mv v hz 300 300 150 mv c l 50 50 30 pf new16link test switch open drain disable low enable low v load disable high enable high gnd all other tests open new16link definitions: c l = load capacitance: includes jig and probe capacitance. r t = termination resistance: should be equal to z out of the pulse generator. note: 1. diagram shown for input control enable-low and input control disable-high. notes: 1. pulse generator for all pulses: rate 10mhz; t f 2.5ns; t r 2.5ns. 2. pulse generator for all pulses: rate 10mhz; t f 2ns; t r 2ns. pulse width
8 extended commercial temperature range idt74alvch16701 3.3v cmos 18-bit read/write buffer with bus-hold *to search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2. the idt logo is a registered trademark of integrated device technology, inc. ordering information corporate headquarters for sales: 2975 stender way 800-345-7015 or 408-727-6116 santa clara, ca 95054 fax: 408-492-8674 www.idt.com* idt xx alvc xxx xx package device type temp. range pv pa pf 16 74 shrink small outline package (so56-1) thin shrink small outline package (so56-2) thin very small outline package (so56-3) 18-bit read/write buffer with bus-hold -40c to +85c x xx family bus-hold 701 bus-hold double-density with resistors, 24ma h
|
